This invention relates generally to semiconductor product fabrication, and more particularly the invention relates to devices and methods for monitoring deleterious effects on semiconductor wafers due to charge induced damage during fabrication of integrated circuits and other semiconductor devices.
It is known that semiconductor processes such as ion implantation, plasma etching, and other charged beam processing may cause damage to semiconductor wafers and the devices and circuits fabricated therein. To assess the damage-generating tendency of such processes, and to determine safe integrated circuit layout guidelines, the semiconductor industry has used polysilicon capacitors with varying gate oxide-field oxide ratios, edge-area ratios, and the like to statistically assess the manner and extent to which these parameters influence the degree of damage, and to develop or select more benign process options. However, due to the indirect nature of this monitoring procedure which relies on compiling frequency of oxide breakdown statistics, the results have frequently been inconclusive and confusing.
It is also known that damage to MOS transistors, capacitors, and other IC device structures is caused by the passage of current through the insulating layers, generally oxides or their derivatives, incorporated in the make-up of such structures. In particular, the quality and reliability of gate dielectrics employed in MOS transistors is generally assessed by the magnitude of the charge per unit area, Qbd, which oxides withstand before breakdown. Degradation of other device parameters, such as MOS transistor threshold voltage, transconductance, sub-threshold leakage, and junction leakage is also directly related to the amount of charge passed through the gate oxide.
To assess the ability of a charged particle process medium to inflict damage to IC device structures, it is, therefore, essential to know the magnitude of the charge fluxes collected by electrodes, such as gate electrodes and interconnect metalization connected to gate electrodes which are exposed to charge fluxes during integrated circuit processing. Moreover, since the passage of charge through oxides requires sufficiently high potentials to be developed across the oxides, the prediction of damage in IC structures during integrated circuit processing requires that the charge-density vs. voltage, J-V characteristics (where V=Vsurface-Vsubstrate) of the various media employed in wafer processing be accurately determined.
Although a variety of probes, generally known as Langmuir probes, have been developed and are used to characterize the J-V characteristics of charged particle media, an example of which is shown in FIG. 1, they suffer from the limitation that they do not measure the J-V characteristic at the wafer surface, where a variety of mechanisms, such as emission of secondary electrons or charged and neutral species from photoresist covering a portion of the wafer surface during these processes, change the local plasma density and the local plasma J-V characteristics. Moreover, such integrated circuit processes often exhibit substantial and deleterious non-uniformities over the wafer surface, which are difficult and very time consuming to characterize using a single probe. Consequently, to characterize these effects and their impact on the local plasma J-V characteristics, it is essential that the J-V probes be incorporated into the wafer surface, and frequently replicated over the surface of the wafer.
Practical application of conventional wafer surface probes, which require power and signal connections, is also precluded in integrated circuit manufacturing by the difficulty of supplying power and retrieving signals in an electrically-hostile plasma environment, compounded by rotating wafer supports and wafer transports employing complex robotic wafer handling mechanisms.
Lukaszek U.S. Pat. No. 5,315,145 discloses a charge monitoring device which can be fabricated in a semiconductor wafer for monitoring either positive or negative surface charge by shunting undesired charge on a charge collecting electrode to ground. The selected charge on the charge collecting electrode alters the threshold voltage of the EEPROM device.
The present invention is directed to a practical tool for characterizing the J-V characteristics of wafer charging media in such environments, including a self-contained, discrete, passive plasma wafer probe, which requires no power or connections to the wafer.